It is necessary to reduce the line width in order to manufacture a highly integrated semiconductor device. However, the operation voltage of the semiconductor device is fixed by a specification standard.
Therefore, it can be difficult to design processes for maintaining the reliability of the device. Specifically, hot carrier and negative bias temperature instability (NBTI) have a strong impact on semiconductor manufacturing, and it can be difficult to provide manufacturing conditions addressing these issues. In particular, because hot carrier injection (HCI) characteristic and negative bias temperature instability (NBTI) characteristic have conflicting trends in accordance with the influence of nitrogen under a condition where a NO gate insulating layer of a single structure is applied, the limits of improved reliability and yield are expected to be reached.
Recently, the thickness of the gate oxide layer of a semiconductor device composed of a core region and an input/output (I/O) region has doubled in response to the operation voltage.
FIGS. 1A to 1D illustrate a conventional method of forming a gate insulating layer of a semiconductor device.
As illustrated in FIG. 1A, a first gate oxide layer 12 is grown on the entire surface of a semiconductor substrate 11 where a field oxide layer (FOX) is formed.
As illustrated in FIG. 1B, an I/O region is covered with a photoresist (PR) layer 13 to remove the first gate oxide layer 12 from a core region by performing a wet etching process.
As illustrated in FIG. 1C, after removing the PR layer 13, a second gate oxidation process is performed to grow a thin second gate oxide layer 14 on the semiconductor substrate 11 of the core region. At this time, the I/O region is additionally oxidized under the first gate oxide layer 12 to form the second gate oxide layer 14 such that the I/O region includes the first gate oxide layer 12 and the second gate oxide layer 14 to form a thick gate oxide layer.
As illustrated in FIG. 1D, nitrogen annealing is performed to form an N-rich oxide layer 15 containing a large amount of nitrogen on the interface between each gate oxide layer and the semiconductor substrate 11. The gate oxide layer structure in which the N-rich oxide layer 15 is formed is referred to as an NO gate oxide layer.
The NO gate oxide layer has strong tolerance against the hot carrier issues of the I/O NMOS. Specifically, during the operation of a transistor, an electro-hole pair (EHP) is generated in the leading end of a drain adjacent to the gate oxide layer by a strong electric field between source/drain and electron injection to the gate insulating layer is generated by the electric field of the gate electrode.
At this time, since the Si—N combination formed on the interface of the NO gate oxide layer has high stability with respect to electron injection in comparison with the Si—O combination, it is possible to improve a hot carrier characteristic.
On the other hand, the NO gate oxide layer applied to I/O PMOS is vulnerable to the NBTI, which is because surplus nitrogen contained in the insulating layer operates as the site of hole generation during the operation of a transistor.
Therefore, due to the increase in a threshold voltage and the reduction in driving current, the life of a product is reduced. Therefore, in order to simultaneously correspond to the HCI characteristic and the NBTI characteristic, the I/O NMOS is preferably formed of the NO gate oxide layer and the I/O PMOS is preferably formed of a pure SiO2 layer.